The widespread use of multichip module (MCM) technologies has been inhibited by the poor yield and infant mortality of untested and unbumed-in bare chips. Whereas a single chip package approach has a packaged part yield equal to that of the product of the assembly yield and the chip yield, multichip approaches have packaged part yields equal to the product of the MCM assembly yield and each of the chip yields. A single chip package with an assembly yield of 95% and a die yield of 95% has a package yield of just over 90%. A four chip MCM with the same assembly and die yields has a package yield of less than 80%, and an eight chip MCM with similar yields has a package yield of about 60%. In MCM designs for which rework is impractical, higher final package yields are required and can only be achieved with higher chip yields.
Infant mortality failures create similar concerns. For single chip packaging, individual packaged parts can be burned-in, i.e., powered with active or passive signals on each component I/O (input/output) pad at an elevated temperature to accelerate a significant percentage of latent chip defects that can be identified prior to component use. Bare chips are generally not subjected to burn-in testing prior to use in a multichip assembly.
Growth of the multichip module (MCM) market is thus limited by a lack of low cost known good die (KGD). KGD are singulated die (bare chips) tested and verified to the manufacturer's specification. KGD are functionally equal to packaged counterparts but have significantly higher costs. Currently, KGD have been cost effective only for the most demanding MCM designs.
High density interconnect (HDI) is a high performance chip packaging technology wherein sequential layers of metallization on polymer are used to interconnect chip pads with high chip density, controlled impedance, and the elimination of the need for solder bump, wirebond, or TAB (tape automated bond) processing. In one form of HDI circuit module, an adhesive-coated polymer film overlay having via openings covers a plurality of integrated circuit chips in chip wells on an underlying substrate. The polymer film provides an insulated layer upon which is deposited a metallization pattern for interconnection of individual circuit chips through the vias. Methods for performing a HDI process using overlays are further described in Eichelberger et al., U.S. Pat. No. 4,783,695, issued Nov. 8, 1988, and in Eichelberger et al., U.S. Pat. No. 4,933,042, issued Jun. 12, 1990. Multiple layers of polymer overlays and metallization patterns are typically applied.
Cole et al., "Fabrication and Structures of Circuit Modules with Flexible Interconnect Layers," U.S. application Ser. No. 08/321,346, filed Oct. 11, 1994, describes a method for fabricating a circuit module using a flexible interconnect layer including a metallized base insulative layer and an outer insulative layer. At least one circuit chip having chip pads is attached to the base insulative layer and vias are formed in the outer and base insulative layers to expose selected portions of the base insulative layer metallization and the chip pads. A patterned outer metallization layer is applied over the outer insulative layer extending through selected ones of the vias to interconnect selected ones of the chip pads and selected portions of the base insulative layer metallization. Because of the metallized layer on the flexible interconnect layer, the number of overlays necessary to achieve the desired interconnections can be reduced and thus the volume and weight of a circuit module can be lowered.